By Al-Zanaidi M.
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Extra resources for 1D-grid generation by monotone iteration discretization
When the positive edge of the clock occurs, the second always block will execute and assign the value of nextState to currentState and then wait again for the next positive edge of clock or negative edge of reset. Since currentState just changed to 1, the first alway block will execute and calculate a new value for out and nextState. out will become 1, and nextState will become 3 if in remains 1. If in becomes 0, the first always block will execute again, recalculating out and nextState independent of the clock edge; nextState will become 0, and out will become 0.
The always statement, introduced here, is the basis for modeling behavior. The always statement, essentially a “while (TRUE)” statement, includes one or more procedural statements that are repeatedly executed. These procedural statements execute much like you would expect a software program to execute: changing register values using the “=” assignment, and executing loops and conditional expressions. Note that within the always statement, all assignments using “=” are made to entities declared as registers.
3. Wires need to be declared when connecting modules together. Here, wires w1 through w5, declared on line two of the example, specify the interconnection. We can see that output register A in module test_bToESeg is connected to an output of the module. The ports are specified and connected in order. In module testBench, A is the second port (eSeg is the first) and is connected to wire w2 (the second port in the list of ports), which is also connected to port A on module binaryToESeg. Inside module binaryToESeg, that port is connected to gates g2 and g4.